This invention relates generally to electronic circuits and, more particularly, to phase splitter circuits for generating true and complement logic signals from an input logic signal.
Dynamic logic circuits are based on electrical charge storage and transfer. One or more circuit nodes are used to store electrical charge. The nodes are typically charged to one voltage level (i.e., precharged) during a precharge operation, and selectively charged (e.g., discharged) to another voltage level during a subsequent evaluation operation dependent upon one or more input signals. For example, nodes of dynamic logic circuits are commonly precharged to a high voltage level when a synchronizing clock signal is at one voltage level (e.g., a low voltage level), and selectively discharged to a low voltage level dependent upon input signals when the clock signal transitions to another voltage level (e.g., a high voltage level).
Dynamic logic circuits typically operate faster, and require less integrated circuit die areas, than similar static logic circuits. On the other hand, dynamic logic circuits are also more sensitive to noise, clock signal timing, signal race conditions, and semiconductor process variations. Due to their drawbacks, dynamic logic circuits are often relegated to highly-specialized hand-tuned circuits, typically those along critical timing paths.
Many different types of logic circuits (e.g., memory array circuits) require logic signals and their complements (i.e., xe2x80x9ctruexe2x80x9d and complement signals). When only true signals are provided, the complement signals must be generated. Static logic signals transition between defined logic levels, and generating a complement of a static logic signal requires only a relatively simple inverter gate (i.e., inverter).
Dynamic logic signals, on the other hand, are valid only during an evaluation phase of a clock signal. Further, true and complement signals must typically be valid at substantially the same time during the evaluation phase for proper dynamic circuit operation. For these reasons, generating a complement of a dynamic logic signal typically requires a more sophisticated true/complement signal generator (i.e., a phase splitter circuit) producing true and corresponding complement dynamic logic signals that are valid at substantially the same time during an evaluation phase of a clock signal.
When a phase splitter requires different amounts of time to produce true and corresponding complement signals dependent upon their logic values, the longest amount of time must typically be allowed for availability of the true and complement signals. As a result, an upper performance limit of a logic circuit using the true and complement signals is reduced. For example, assume a phase splitter requires one amount of time to produce a logic xe2x80x981xe2x80x99 true signal and the corresponding logic xe2x80x980xe2x80x99 complement signal, and a longer amount of time to produce a logic xe2x80x980xe2x80x99 true signal and the corresponding logic xe2x80x981xe2x80x99 complement signal. A logic circuit using the true and complement signals must allow the longer amount of time for availability of the true and complement signals and, as a result, an upper performance limit of the logic circuit is reduced.
As mentioned above, dynamic logic circuits are more sensitive to noise than static logic circuits. In addition, noise signals on signal lines are capacitively coupled to charge storage nodes, and are additive.
It would thus be advantageous to have a phase splitter circuit that generates relatively little noise during operation, and produces true and complement dynamic logic signals that are valid at substantially the same time during an evaluation phase of a clock signal independent of their logic values.
A phase splitter circuit is disclosed including a clock delay section, a signal converter section and a signal generator section. The clock delay section receives a clock signal and produces a first delayed clock signal and a second delayed clock signal. The first and second delayed clock signals are time delayed versions of the received clock signal, and the second delayed clock signal is delayed in time to a greater extent than the first delayed clock signal.
The signal converter section receives a static logic signal, the clock signal and the first delayed clock signal, and converts the static logic signal to a dynamic logic signal dependent upon the clock signal and the first delayed clock signal. The signal generator section receives the dynamic logic signal, the first delayed clock signal and the second delayed clock signal, and produces a pair of complementary dynamic logic output signals dependent upon the dynamic logic signal, the first delayed clock signal, and the second delayed clock signal, wherein one of the complementary dynamic logic output signals has a logic value equal to that of the static logic signal during an evaluation phase of the clock signal. The phase splitter circuit produces the complementary dynamic logic output signals at substantially the same time, and generates relatively little noise during operation.
A method is described for generating a pair of complementary dynamic logic signals from a static logic signal. The method includes using the clock signal to produce the above described first and second delayed clock signals. The clock signal and the first delayed clock signal are used to convert the static logic signal to a dynamic logic signal. The dynamic logic signal, the first delayed clock signal and the second delayed clock signal are used to produce the pair of complementary dynamic logic signals, wherein one of the complementary dynamic logic signals has a logic value equal to that of the static logic signal during an evaluation phase of the clock signal.